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upgrade_of_fw_status

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upgrade_of_fw_status [2018/06/19 08:05]
DAQ user
upgrade_of_fw_status [2018/06/19 08:33]
DAQ user [State machine changes]
Ligne 6: Ligne 6:
   - ''​Clear separation of acquisition and data transfer'':​ The firmware is not controlling the acquisition time, it just throws a BUSY when one TDC fifo is ALmost Full (25 over 32). The BUSYs are collected by the MDCC board that terminates the acquisition window when one busy is seen and do not restart a window until all BUSYs are low.   - ''​Clear separation of acquisition and data transfer'':​ The firmware is not controlling the acquisition time, it just throws a BUSY when one TDC fifo is ALmost Full (25 over 32). The BUSYs are collected by the MDCC board that terminates the acquisition window when one busy is seen and do not restart a window until all BUSYs are low.
   - ''​Data transmit per channel'':​ Once the acquisition window is end, a BUSY is set per FEB until the data transfer is completed. It consists first to an Event packet containing the GTC (window count) and the Absolute BCID (readout time 200 ns steps). Then TDCs are scanned one by one , if not empty a channel packet is sent. Once all TDCs are browsed, BUSY is released and the FEB is in IDLE for the next window.   - ''​Data transmit per channel'':​ Once the acquisition window is end, a BUSY is set per FEB until the data transfer is completed. It consists first to an Event packet containing the GTC (window count) and the Absolute BCID (readout time 200 ns steps). Then TDCs are scanned one by one , if not empty a channel packet is sent. Once all TDCs are browsed, BUSY is released and the FEB is in IDLE for the next window.
-  - ''​ Trigger Mode '':​+  - ''​ Trigger Mode '': ​If the trigger mode is set, at data transfer stage, the trigger TDC (0) is first check, if the FIFO is empty, all FIFOs are cleared, BUSY is released and the FEB  go back in IDLE state. It minimizes the dead time and only events with external trigger are transmitted. 
 + 
 + 
 +===== Performances and hardware changes ===== 
 + 
 +  * The data transfer per channel is less performant but compulsory since there is not enough space in CYCLONE II to handle large enough transfer FIFO for all channels. Nevertheless since TCPIP packets are adding 54 bytes of header it mights be a large overhead if only few channels are acquired in a TDC 
 +  * The maximum bandwidth of the Wiznet is indeed 50 Mbits/s and a //feature// of the chips decreases it to 33 Mbits/s (including TCPIP header) 
 +  * When we use Raspberry PI with USB ethernet interface the badnwidth is even decreased to 12 Mbit/s due to the sharing of the USB bus on those SOCs PC. We got much better performances (80 Mbits/s for 4 FEBs) connecting all FEBs to a switch and the switch to an additional Ethernet card on a standard PC. It will require to buy small PC with at least 2 ethernet card that can be installed in GIF.  
 + 
 + 
  
 ===== Data Transfer ===== ===== Data Transfer =====
upgrade_of_fw_status.txt · Dernière modification: 2018/06/19 08:33 par DAQ user