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representation_asic_json [2020/01/09 08:58] (Version actuelle)
DAQ user créée
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 +======= Representation des ASICs =======
 +
 +Un state est un nom une version et une liste d'​asic. En cas de modification d'un parametre, une nouvelle entree des asics modifies est faite.
 +La liste et le numero de version sont aussi aussi modifies ​
 +
 +Chaque ASIC est identifie par son numero de DIF et son numero d'​ASIC,​ un tag ''​address''​ peut egalement etre utilise. Les valeurs de chargement du slow control
 +sont enumerees sou le tag ''​slc''​. Elles correspondent aux parametres decrits dans les documentations des deux chips.
 +
 +===== PETIROC =====
 +
 +Le numero de DIF correspond a l'​adresse IP:
 +
 +3594 = 0xe0a => 15.10 et l'​adresse IP est 192.168.10.15
 +
 +
 +  {"​dif":​ 3594, "​num":​ 1, 
 +  "​slc": ​
 +        {"​6bDac":​ [1, 1, 1, 1, 30, 28, 31, 30, 30, 25, 30, 38, 39, 30, 33, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1], 
 +         "​Cf0_1p25pF":​ 0, "​Cf1_2p5pF":​ 0, "​Cf2_200fF":​ 0, "​Cf3_100fF":​ 0, "​Choice_Trigger_Out":​ 0, "​DIS_razchn_ext":​ 0, "​DIS_razchn_int":​ 1, 
 +         "​DIS_trig_mux":​ 1, "​DIS_triggers":​ 0, "​DacDelay":​ 31, "​EN10bDac":​ 1, "​EN_80M":​ 0, "​EN_NOR32_charge":​ 0, "​EN_NOR32_time":​ 1, "​EN_adc":​ 0,
 +         "​EN_bias_6bit_dac":​ 1, "​EN_bias_charge":​ 0, "​EN_bias_dac_delay":​ 0, "​EN_bias_discri":​ 1, "​EN_bias_discri_adc_charge":​ 0, "​EN_bias_discri_adc_time":​ 0, 
 +         "​EN_bias_discri_charge":​ 0, "​EN_bias_pa":​ 1, "​EN_bias_ramp_delay":​ 0, "​EN_bias_sca":​ 0, "​EN_bias_tdc":​ 0, "​EN_discri_delay":​ 0, "​EN_dout_oc":​ 0, 
 +         "​EN_fast_lvds_rec":​ 1, "​EN_slow_lvds_rec":​ 1, "​EN_temp_sensor":​ 0, "​EN_transmit":​ 0, "​EN_transmitter":​ 0, 
 +         "​InputDac":​ [255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255], 
 +         "​InputDacCommand":​ [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1], 
 +         "​MaskDiscriCharge":​ [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1], 
 +         "​MaskDiscriTime":​ [1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1],
 +         "​ON_OFF_1mA":​ 1, "​ON_OFF_2mA":​ 1, "​ON_OFF_input_dac":​ 1, "​ON_OFF_otaQ":​ 0, "​ON_OFF_ota_mux":​ 0, "​ON_OFF_ota_probe":​ 0, "​PA_ccomp_0":​ 1, "​PA_ccomp_1":​ 1, "​PA_ccomp_2":​ 1, "​PA_ccomp_3":​ 1,
 +         "​PP10bDac":​ 0, "​PP_adc":​ 0, "​PP_bias_6bit_dac":​ 0, "​PP_bias_charge":​ 0, "​PP_bias_dac_delay":​ 0, "​PP_bias_discri":​ 0, "​PP_bias_discri_adc_charge":​ 0, "​PP_bias_discri_adc_time":​ 0, 
 +         "​PP_bias_discri_charge":​ 0, "​PP_bias_pa":​ 0, "​PP_bias_ramp_delay":​ 0, "​PP_bias_sca":​ 0, "​PP_bias_tdc":​ 0, "​PP_discri_delay":​ 0, "​PP_fast_lvds_rec":​ 0, "​PP_slow_lvds_rec":​ 0, 
 +         "​PP_temp_sensor":​ 0, "​PP_transmitter":​ 0, "​SEL_80M":​ 0, "​VthDiscriCharge":​ 863, "​VthTime":​ 515, "​cmd_polarity":​ 0, "​header":​ 1, "​latch":​ 1, "​sel_starb_ramp_adc_ext":​ 0, "​usebcompensation":​ 0}}
 +
 +===== HARDROC 2 =====
 +
 +==== GRIC board ====
 +
 +Cette fois ci l'​adresse IP est specifiee, 4708=0x1264 ==> 18.100
 +
 +   ​{"​address":​ "​192.168.100.18",​ "​dif":​ 4708, "​num":​ 1, 
 +   "​slc":​ {
 +        "​B0":​ 145, "​B1":​ 250, "​B2":​ 250, "​CLKMUX":​ 1, "​CMDB0FSB1":​ 1, "​CMDB0FSB2":​ 1, "​CMDB0SS":​ 0, "​CMDB1FSB1":​ 1, "​CMDB1FSB2":​ 1, 
 +        "​CMDB1SS":​ 0, "​CMDB2FSB1":​ 0, "​CMDB2FSB2":​ 0, "​CMDB2SS":​ 0, "​CMDB3FSB1":​ 1, "​CMDB3FSB2":​ 1, "​CMDB3SS":​ 0, 
 +        "​CTEST":​ [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], 
 +        "​DACSW":​ 1, "​DISCRI0":​ 1, "​DISCRI1":​ 1, "​DISCRI2":​ 1, "​DISCROROR":​ 1, "​ENOCCHIPSATB":​ 1, "​ENOCDOUT1B":​ 1, "​ENOCDOUT2B":​ 0, 
 +        "​ENOCTRANSMITON1B":​ 1, "​ENOCTRANSMITON2B":​ 0, "​ENTRIGOUT":​ 1, "​EN_OTAQ":​ 1, "​HEADER":​ 1, 
 +        "​MASK0":​ [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1], 
 +        "​MASK1":​ [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1], 
 +        "​MASK2":​ [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1], 
 +        "​OTABGSW":​ 1, "​OTAQ_PWRADC":​ 1, 
 +        "​PAGAIN":​ [128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 
 +                   128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128],
 +        "​PWRONBUFF":​ 1, "​PWRONFSB0":​ 1, "​PWRONFSB1":​ 1, "​PWRONFSB2":​ 1, "​PWRONPA":​ 1, "​PWRONSS":​ 0, "​PWRONW":​ 1, "​QSCSROUTSC":​ 1, "​RAZCHNEXTVAL":​ 0, "​RAZCHNINTVAL":​ 1, 
 +        "​RS_OR_DISCRI":​ 1, "​SCON":​ 1, "​SEL0":​ 1, "​SEL1":​ 0, "​SELENDREADOUT":​ 1, "​SELSTARTREADOUT":​ 1, "​SMALLDAC":​ 0, 
 +        "​SW100F0":​ 1, "​SW100F1":​ 1, "​SW100F2":​ 1, "​SW100K0":​ 1, "​SW100K1":​ 1, "​SW100K2":​ 1, "​SW50F0":​ 1, "​SW50F1":​ 1, "​SW50F2":​ 1, 
 +        "​SW50K0":​ 1, "​SW50K1":​ 1, "​SW50K2":​ 1, "​SWSSC":​ 7, "​TRIG0B":​ 1, "​TRIG1B":​ 0, "​TRIG2B":​ 0, "​TRIGEXTVAL":​ 0}}
 +
 +==== DIF board ====
 +
 +Un tag ''​address''​ est defini pour avoir une approche unifiee: 0.0.0.#​dif ​
 +
 +   {
 +    "​address":​ "​0.0.0.5",​ "​dif":​ 5, "​num":​ 1, 
 +    "​slc": ​
 +     ​{"​B0":​ 170, "​B1":​ 250, "​B2":​ 250, "​CLKMUX":​ 1, "​CMDB0FSB1":​ 1, "​CMDB0FSB2":​ 1, "​CMDB0SS":​ 0, "​CMDB1FSB1":​ 1, "​CMDB1FSB2":​ 1, 
 +      "​CMDB1SS":​ 0, "​CMDB2FSB1":​ 0, "​CMDB2FSB2":​ 0, "​CMDB2SS":​ 0, "​CMDB3FSB1":​ 1, "​CMDB3FSB2":​ 1, "​CMDB3SS":​ 0, 
 +      "​CTEST":​ [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], 
 +      "​DACSW":​ 1, "​DISCRI0":​ 1, "​DISCRI1":​ 1, "​DISCRI2":​ 1, "​DISCROROR":​ 1, "​ENABLED":​ 1, "​ENOCCHIPSATB":​ 1, "​ENOCDOUT1B":​ 1, "​ENOCDOUT2B":​ 0, "​ENOCTRANSMITON1B":​ 1, "​ENOCTRANSMITON2B":​ 0, "​ENTRIGOUT":​ 1, "​EN_OTAQ":​ 1, "​HEADER":​ 1,
 +      "​MASK0":​ [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1], 
 +      "​MASK1":​ [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1], 
 +      "​MASK2":​ [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1], 
 +      "​OTABGSW":​ 1, "​OTAQ_PWRADC":​ 1,
 +      "​PAGAIN":​ [128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128,
 +                   128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128], 
 +      "​PWRONBUFF":​ 1, "​PWRONFSB0":​ 1, "​PWRONFSB1":​ 1, "​PWRONFSB2":​ 1, "​PWRONPA":​ 1, "​PWRONSS":​ 0, "​PWRONW":​ 1, "​QSCSROUTSC":​ 1, "​RAZCHNEXTVAL":​ 0, "​RAZCHNINTVAL":​ 1, 
 +      "​RS_OR_DISCRI":​ 1, "​SCON":​ 1, "​SEL0":​ 1, "​SEL1":​ 0, "​SELENDREADOUT":​ 1, "​SELSTARTREADOUT":​ 1, "​SMALLDAC":​ 0, "​SW100F0":​ 1, "​SW100F1":​ 1, "​SW100F2":​ 1, "​SW100K0":​ 1, "​SW100K1":​ 1, "​SW100K2":​ 1, "​SW50F0":​ 1, "​SW50F1":​ 1, "​SW50F2":​ 1, 
 +      "​SW50K0":​ 1, "​SW50K1":​ 1, "​SW50K2":​ 1, "​SWSSC":​ 7, "​TRIG0B":​ 1, "​TRIG1B":​ 0, "​TRIG2B":​ 0, "​TRIGEXTVAL":​ 0}}
  
representation_asic_json.txt · Dernière modification: 2020/01/09 08:58 par DAQ user