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febv1_debug

Summary of FEB version 1 debugging

Schematic issues

  • Missing control signals on regulator ⇒ by passed hardwarely
  • One missing pull up on NOR32 per ASIC ⇒ Fixed externally
  • HDMI signals direction ⇒ Use alternative signal entries on FPGA and patch MDCC accordingly
  • 11 Mhz calibration clock missing ⇒ oscillator added on spare entry
  • Jitter-cleaner chip unstability ⇒ By passed, used either an additional 40 Mhz oscillator or MDCC clock directly

Issue with high (>24) number of channels

  • Signal TAP (multi channels internal logic analyzer) unstabilties
    • Initially we thought it is firmware related. Lot of time lost in trying to understand fluctuant behaviours
  • Identified the source to a 400 MHz clock unstabilities ⇒ Internal to the FPGA
  • Vcc core drops from 1.1 V to 0.95 V when more than 24 channels used
    • We first change the regulator ⇒ same problem
    • Routing issue: Strip line from regulator to FPGA too resistive ⇒ bring directly the 1.1 V to the FPGA ⇒ SOLVED

First firmwares tested

Mapping

PCB 44 stripsFE2PRPRPR_INremapTDC
T1back211CH21B100
B1back201ch20A101
T2back231ch23E102
B2back221ch22D103
T3back251ch25A114
B3back241ch24F105
T4back271ch27D116
B4back261ch26B117
T5back291ch29A128
B5back281ch28F119
T6back311ch31D1210
B6back301ch30D1511
T7front171ch1A212
B7Front161ch0C113
T8front191ch3B314
B9front181ch2A315
T9front211ch5B516
B9front201ch4A517
T10front231ch7B618
B10front221ch6A619
T11front261ch10C720
B11front241ch8C621
T12Front311ch15C822
B12front281ch12E723
T13back52ch21A2824
B13back42ch20B2825
T14back72ch23D2926
B14back62ch22E2927
T15back92ch25B2928
B15back82ch24C2929
T16back112ch27E3030
B16back102ch26F3031
T17back132ch29B3032
B17back122ch28D3033
T18back152ch31B3134
B18back142ch30C3135
T19front12ch1B2436
B19front02ch0D2437
T20Front32ch3E2538
B20front22ch2F2539
T21front52ch5B2540
B21front42ch4D2541
T22front72ch7F2642
B22front62ch6A2543
T23front102ch10B2644
B23front82ch8D2645
T24front142ch14D2746
B24front122ch12F2747

Carefull: The 2 chips don't have the same mapping

48 channels latched (rising edge only)

Pedestals

FEBv2_1 channel per channel 745460

FEBv2_7 channel per channel 745463

FEBv2_8 channel per channel 745464

FEBv2_8 all channels 745465

Injection tests

Injection board

It is functionnal but no possibility to modulate the FPGA output voltage ⇒ No pedestal/gain curve. Patch with additional buffers will be tested soon

Time calibration feasible.

2018/11/09 Status & plans

* Debugging Petiroc FSM (deadlock). Lengthly due to compilation time with 48 channels (2h)

* Next week:

  • Complete time calibration
  • Re test ToT version
  • Transfer the board to Cern and connect it on the return chamber (additional boards are still in cabling since some components are now missing in the cabling company)
    • Repeat noise and calibration tests
    • Check efficiency curves and position resolution

* Before Xmas break:

  • Check GBT capabilities (No need to have fully debugged readout, but 5 Gb/s transfer + TDCs)
  • Re submit the board with all corrections
    • Confirm all the fixes before submitting V2
    • Will be used for R&D RPCs

2018/11/11 Debugging

Still unstable PETIROC FSM with 48 channels

  • Working with small time window or with low rate, dead lock in all other cases
  • Working with 16 channels
febv1_debug.txt · Dernière modification: 2018/11/12 10:49 par DAQ user